`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    16:17:34 11/03/2011 
// Design Name: 
// Module Name:    axi_router 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module axis_router(
  input               clk,
  input               rst,

  input               s0_tvalid,
  output              s0_tready,
  input   [127:0]     s0_tdata,
  input   [3:0]       s0_tstrb,
  input               s0_tlast,
      
  output              m0_tvalid,
  input               m0_tready,
  output  [127:0]     m0_tdata,
  output  [3:0]       m0_tstrb,
  output              m0_tlast,

  input               s1_tvalid,
  output              s1_tready,
  input   [127:0]     s1_tdata,
  input   [3:0]       s1_tstrb,
  input               s1_tlast,
      
  output              m1_tvalid,
  input               m1_tready,
  output  [127:0]     m1_tdata,
  output  [3:0]       m1_tstrb,
  output              m1_tlast,

  input               s2_tvalid,
  output              s2_tready,
  input   [127:0]     s2_tdata,
  input   [3:0]       s2_tstrb,
  input               s2_tlast,
      
  output              m2_tvalid,
  input               m2_tready,
  output  [127:0]     m2_tdata,
  output  [3:0]       m2_tstrb,
  output              m2_tlast,
  
  input   [7:0]       bus,
  
  input   [31:12]     io_min_1,
  input   [31:12]     io_max_1,
  input   [31:20]     mem_min_1,
  input   [31:20]     mem_max_1,
  input   [63:20]     pmem_min_1,
  input   [63:20]     pmem_max_1,
  input   [7:0]       bus_min_1,
  input   [7:0]       bus_max_1,
  input   [4:0]       device_1,
  
  input   [31:12]     io_min_2,
  input   [31:12]     io_max_2,
  input   [31:20]     mem_min_2,
  input   [31:20]     mem_max_2,
  input   [63:20]     pmem_min_2,
  input   [63:20]     pmem_max_2,
  input   [7:0]       bus_min_2,
  input   [7:0]       bus_max_2,
  input   [4:0]       device_2
  );

  wire          axis_01_tvalid;
  wire          axis_01_tready;

  wire          axis_10_tvalid;
  wire          axis_10_tready;
  
  wire          axis_02_tvalid;
  wire          axis_02_tready;

  wire          axis_20_tvalid;
  wire          axis_20_tready;

  wire          axis_12_tvalid;
  wire          axis_12_tready;

  wire          axis_21_tvalid;
  wire          axis_21_tready;
  
  axis_pcie_dmux #(
    .UP_STREAM_DMUX     (1))
  s0_dmux(
    .clk                (clk              ),
    .rst                (rst              ),
    
    .s_tvalid           (s0_tvalid        ),
    .s_tready           (s0_tready        ),
    .s_tdata            (s0_tdata         ),
    .s_tstrb            (s0_tstrb         ),
    .s_tlast            (s0_tlast         ),

    .m0_tvalid          (axis_01_tvalid   ),
    .m0_tready          (axis_01_tready   ),
    .m1_tvalid          (axis_02_tvalid   ),
    .m1_tready          (axis_02_tready   ),

    .bus                (bus              ),
    
    .io_min_0           (io_min_1         ),
    .io_max_0           (io_max_1         ),
    .mem_min_0          (mem_min_1        ),
    .mem_max_0          (mem_max_1        ),
    .pmem_min_0         (pmem_min_1       ),
    .pmem_max_0         (pmem_max_1       ),
    .bus_min_0          (bus_min_1        ),
    .bus_max_0          (bus_max_1        ),
    .device_0           (device_1         ),

    .io_min_1           (io_min_2         ),
    .io_max_1           (io_max_2         ),
    .mem_min_1          (mem_min_2        ),
    .mem_max_1          (mem_max_2        ),
    .pmem_min_1         (pmem_min_2       ),
    .pmem_max_1         (pmem_max_2       ),
    .bus_min_1          (bus_min_2        ),
    .bus_max_1          (bus_max_2        ),
    .device_1           (device_2         )
  );

  axis_pcie_dmux 
  s1_dmux(
    .clk                (clk              ),
    .rst                (rst              ),
    
    .s_tvalid           (s1_tvalid        ),
    .s_tready           (s1_tready        ),
    .s_tdata            (s1_tdata         ),
    .s_tstrb            (s1_tstrb         ),
    .s_tlast            (s1_tlast         ),

    .m0_tvalid          (axis_12_tvalid   ),
    .m0_tready          (axis_12_tready   ),
    .m1_tvalid          (axis_10_tvalid   ),
    .m1_tready          (axis_10_tready   ),

    .bus                (bus              ),
    
    .io_min_0           (io_min_2         ),
    .io_max_0           (io_max_2         ),
    .mem_min_0          (mem_min_2        ),
    .mem_max_0          (mem_max_2        ),
    .pmem_min_0         (pmem_min_2       ),
    .pmem_max_0         (pmem_max_2       ),
    .bus_min_0          (bus_min_2        ),
    .bus_max_0          (bus_max_2        ),
    .device_0           (device_2         ),

    .io_min_1           (20'h00000        ),
    .io_max_1           (20'hFFFFF        ),
    .mem_min_1          (12'h000          ),
    .mem_max_1          (12'hFFF          ),
    .pmem_min_1         (44'h00000000000  ),
    .pmem_max_1         (44'hFFFFFFFFFFF  ),
    .bus_min_1          (8'h00            ),
    .bus_max_1          (8'hFF            ),
    .device_1           (5'b00000         )
  );

  axis_pcie_dmux 
  s2_dmux(
    .clk                (clk              ),
    .rst                (rst              ),
    
    .s_tvalid           (s2_tvalid        ),
    .s_tready           (s2_tready        ),
    .s_tdata            (s2_tdata         ),
    .s_tstrb            (s2_tstrb         ),
    .s_tlast            (s2_tlast         ),

    .m0_tvalid          (axis_21_tvalid   ),
    .m0_tready          (axis_21_tready   ),
    .m1_tvalid          (axis_20_tvalid   ),
    .m1_tready          (axis_20_tready   ),

    .bus                (bus              ),
    
    .io_min_0           (io_min_1         ),
    .io_max_0           (io_max_1         ),
    .mem_min_0          (mem_min_1        ),
    .mem_max_0          (mem_max_1        ),
    .pmem_min_0         (pmem_min_1       ),
    .pmem_max_0         (pmem_max_1       ),
    .bus_min_0          (bus_min_1        ),
    .bus_max_0          (bus_max_1        ),
    .device_0           (device_1         ),

    .io_min_1           (20'h00000        ),
    .io_max_1           (20'hFFFFF        ),
    .mem_min_1          (12'h000          ),
    .mem_max_1          (12'hFFF          ),
    .pmem_min_1         (44'h00000000000  ),
    .pmem_max_1         (44'hFFFFFFFFFFF  ),
    .bus_min_1          (8'h00            ),
    .bus_max_1          (8'hFF            ),
    .device_1           (5'b00000         )
  );
  
  axis_mux #(
    .DWIDTH     (128),
    .KWIDTH     (4))
  m0_mux(
    .clk        (clk        ),
    .rst        (rst        ),
                 
    .s0_tvalid  (axis_10_tvalid  ),
    .s0_tready  (axis_10_tready  ),
    .s0_tdata   (s1_tdata   ),
    .s0_tkeep   (s1_tstrb   ),
    .s0_tlast   (s1_tlast   ),
                 
    .s1_tvalid  (axis_20_tvalid  ),
    .s1_tready  (axis_20_tready  ),
    .s1_tdata   (s2_tdata   ),
    .s1_tkeep   (s2_tstrb   ),
    .s1_tlast   (s2_tlast   ),
                 
    .m_tvalid   (m0_tvalid   ),
    .m_tready   (m0_tready   ),
    .m_tdata    (m0_tdata    ),
    .m_tkeep    (m0_tstrb    ),
    .m_tlast    (m0_tlast    )
  );

  axis_mux #(
    .DWIDTH     (128),
    .KWIDTH     (4))
  m1_mux(
    .clk        (clk        ),
    .rst        (rst        ),
                 
    .s0_tvalid  (axis_01_tvalid  ),
    .s0_tready  (axis_01_tready  ),
    .s0_tdata   (s0_tdata   ),
    .s0_tkeep   (s0_tstrb   ),
    .s0_tlast   (s0_tlast   ),
                 
    .s1_tvalid  (axis_21_tvalid  ),
    .s1_tready  (axis_21_tready  ),
    .s1_tdata   (s2_tdata   ),
    .s1_tkeep   (s2_tstrb   ),
    .s1_tlast   (s2_tlast   ),
                 
    .m_tvalid   (m1_tvalid   ),
    .m_tready   (m1_tready   ),
    .m_tdata    (m1_tdata    ),
    .m_tkeep    (m1_tstrb    ),
    .m_tlast    (m1_tlast    )
  );

  axis_mux #(
    .DWIDTH     (128),
    .KWIDTH     (4))
  m2_mux(
    .clk        (clk        ),
    .rst        (rst        ),
                 
    .s0_tvalid  (axis_02_tvalid  ),
    .s0_tready  (axis_02_tready  ),
    .s0_tdata   (s0_tdata   ),
    .s0_tkeep   (s0_tstrb   ),
    .s0_tlast   (s0_tlast   ),
                 
    .s1_tvalid  (axis_12_tvalid  ),
    .s1_tready  (axis_12_tready  ),
    .s1_tdata   (s1_tdata   ),
    .s1_tkeep   (s1_tstrb   ),
    .s1_tlast   (s1_tlast   ),
                 
    .m_tvalid   (m2_tvalid   ),
    .m_tready   (m2_tready   ),
    .m_tdata    (m2_tdata    ),
    .m_tkeep    (m2_tstrb    ),
    .m_tlast    (m2_tlast    )
  );
  
endmodule

